1. Field of the Invention
The present invention relates to integrated circuit fabrication techniques, and more particularly to a method for interconnecting integrated circuit chip packages having package leads on very close centers to an interconnect board such that the leads are formed and soldered on very close centers, yet are protected from handling damage and lead-to-lead shorting.
2. Description of the Prior Art
The trend in integrated circuit manufacture is toward greater intergration of functions on a single chip. This results in more gates on the chips and higher input/output (I/O) pin counts. I/O requirements of over 200 leads on a single chip are projected. Packaging of these chips into a single chip package is desirable due to the high cost of the chip, the requirement for testing the chip before committing to an assembly, and the desire to easily remove and replace a defective chip in an assembly. However, current packages require extremely large sizes due to the package perimeter required for the large number of leads. A 200 lead flatpackage with leads on four sides with a standard 50 mil lead spacing would have a size over 1.5 inches square, resulting in an expensive, low-density package. Lead centers as small as 12.5 or 10 mils on a chip package are desirable. As the lead center decrease, however, the leads become more fragile and susceptible to being bent which causes alignment problems when mounting the package to a board, or even electrical shorting if the leads are so badly bent as to touch one another. Also, after the package is mounted the fragile leads are still susceptible to handling damage and possible shorts.